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rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a complete 12-bit 1.5/3.0/10.0 msps monolithic a/d converters ad9221/ad9223/ad9220 functional block diagram vina capt capb sense otr bit 1 (msb) bit 12 (lsb) vref dvss avss cml ad9221/ad9223/ad9220 sha digital correction logic output buffers vinb 1v refcom 5 5 4 4 3 3 3 12 dvdd avdd clk mode select mdac3 gain = 4 mdac2 gain = 8 mdac1 gain = 16 a/d a/d a/d a/d features monolithic 12-bit a/d converter product family family members are: ad9221, ad9223, and ad9220 flexible sampling rates: 1.5 msps, 3.0 msps and 10.0 msps low power dissipation: 59 mw, 100 mw and 250 mw single +5 v supply integral nonlinearity error: 0.5 lsb differential nonlinearity error: 0.3 lsb input referred noise: 0.09 lsb complete: on-chip sample-and-hold amplifier and voltage reference signal-to-noise and distortion ratio: 70 db spurious-free dynamic range: 86 db out-of-range indicator straight binary output data 28-lead soic and 28-lead ssop suited for communication systems employing direct-if down conversion since the sha in the differential input mode can achieve excellent dynamic performance far beyond its specified nyquist frequency. 2 a single clock input is used to control all internal conversion cycles. the digital output data is presented in straight binary output format. an out-of-range (otr) signal indicates an overflow condition which can be used with the most significant bit to determine low or high overflow. product highlights the ad9221/ad9223/ad9220 family offers a complete single- chip sampling 12-bit, analog-to-digital conversion function in pin-compatible 28-lead soic and ssop packages. flexible sampling ratesthe ad9221, ad9223 and ad9220 offer sampling rates of 1.5 msps, 3.0 msps and 10.0 msps, respectively. low power and single supplythe ad9221, ad9223 and ad9220 consume only 59 mw, 100 mw and 250 mw, respec- tively, on a single +5 v power supply. excellent dc performance over temperaturethe ad9221/ ad9223/ad9220 provide 12-bit linearity and temperature drift performance. 1 excellent ac performance and low noisethe ad9221/ ad9223/ad9220 provides better than 11.3 enob performance and has an input referred noise of 0.09 lsb rms. 2 flexible analog input rangethe versatile onboard sample- and-hold (sha) can be configured for either single ended or differ- ential inputs of varying input spans. notes 1 excluding internal voltage reference. 2 depends on the analog input configuration. product description the ad9221, ad9223, and ad9220 are a generation of high performance, single supply 12-bit analog-to-digital converters. each device exhibits true 12-bit linearity and tempera ture drift performance 1 as well as 1 1.5 bit or better ac performa nce. 2 the ad9221/ad9223/ad9220 share the same interface options, package, and pinout. thus, the product family provides an upward or downward component selection path based on per- formance, sample rate and power. the devices differ with re- spect to their specified sampling rate and power consumption which is reflected in their dynamic performance over frequency. the ad9221/ad9223/ad9220 combine a low cost, high speed cmos process and a novel architecture to achieve the resolution and speed of existing hybrid and monolithic implementations at a fraction of the power consumption and cost. each device is a complete, monolithic adc with an on-chip, high performance, low noise sample-and-hold amplifier and programmable voltage reference. an external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. the devices use a multistage differential pipelined architecture with digital output error correction logic to provide 12-bit accuracy at the specified data rates and to guarantee no missing codes over the full operating tempera ture range. the input of the ad9221/ad9223/ad9220 is highly flexible, allowing for easy interfacing to imaging, communications, medi- cal, and data-acquisition systems. a truly differential input structure allows for both single-ended and differential input interfaces of varying input spans. the sample-and-hold (sha) amplifier is equally suited for both multiplexed systems that switch full-scale voltage levels in successive channels as well as sampling single-channel inputs at frequencies up to and beyond the nyquist rate. also, the ad9221/ad9223/ad9220 is well one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999
rev. c C2C ad9221/ad9223/ad9220Cspecifications dc specifications parameter ad9221 ad9223 ad9220 units resolution 12 12 12 bits min max conversion rate 1.5 3 10 mhz min input referred noise (typ) v ref = 1 v 0.23 0.23 0.23 lsb rms typ v ref = 2.5 v 0.09 0.09 0.09 lsb rms typ accuracy integral nonlinearity (inl) 0.4 0.5 0.5 lsb typ 1.25 1.25 1.25 lsb max differential nonlinearity (dnl) 0.3 0.3 0.3 lsb typ 0.75 0.75 0.75 lsb max inl 1 0.6 0.6 0.7 lsb typ dnl 1 0.3 0.3 0.35 lsb typ no missing codes 12 12 12 bits guaranteed zero error (@ +25 c) 0.3 0.3 0.3 % fsr max gain error (@ +25 c) 2 1.5 1.5 1.5 % fsr max gain error (@ +25 c) 3 0.75 0.75 0.75 % fsr max temperature drift zero error 2 2 2 ppm/ c typ gain error 2 26 26 26 ppm/ c typ gain error 3 0.4 0.4 0.4 ppm/ c typ power supply rejection avdd , dvdd (+5 v 0.25 v) 0.06 0.06 0.06 % fsr max analog input input span (with v ref = 1.0 v) 2 2 2 v p-p min input span (with v ref = 2.5 v) 5 5 5 v p-p max input (vina or vinb) range 0 0 0 v min avdd avdd avdd v max input capacitance 16 16 16 pf typ internal voltage reference output voltage (1 v mode) 1 1 1 volts typ output voltage tolerance (1 v mode) 14 14 14 mv max output voltage (2.5 v mode) 2.5 2.5 2.5 volts typ output voltage tolerance (2.5 v mode) 35 35 35 mv max load regulation 4 2.0 2.0 1.5 mv max reference input resistance 5 5 5 k w typ power supplies supply voltages avdd +5 +5 +5 v ( 5% avdd operating) dvdd +2.7 to +5.25 +2.7 to +5.25 +5 ( 5%) v supply current iavdd 14.0 26 58 ma max 11.8 20 48 ma typ idvdd 0.5 0.5 12 ma max 0.02 0.02 10 ma typ power consumption 59.0 100 250 mw typ 70.0 130 310 mw max notes 1 v ref =1 v. 2 including internal reference. 3 excluding internal reference. 4 load regulation with 1 ma load current (in addition to that required by the ad9220/ad9221/ad9223). specification subject to change without notice. (avdd = +5 v, dvdd = +5 v, f sample = max conversion rate, v ref = 2.5 v, vinb = 2.5 v, t min to t max unless otherwise noted)
ac specifications parameters ad9221 ad9223 ad9220 units max conversion rate 1.5 3.0 10.0 mhz min dynamic performance input test frequency 1 (vina = C0.5 dbfs) 100 500 1000 khz signal-to-noise and distortion (sinad) 70.0 70.0 70 db typ 69.0 68.5 68.5 db min effective number of bits (enobs) 11.3 11.3 11.3 db typ 11.2 11.1 11.1 db min signal-to-noise ratio (snr) 70.2 70.0 70.2 db typ 69.0 68.5 69.0 db min total harmonic distortion (thd) C83.4 C83.4 C83.7 db typ C77.5 C76.0 C76.0 db max spurious free dynamic range (sfdr) 86.0 87.5 88.0 db typ 79.0 77.5 77.5 db max input test frequency 2 (vina = C0.5 dbfs) 0.50 1.50 5.0 mhz signal-to-noise and distortion (sinad) 69.9 69.4 67.0 db typ 69.0 68.0 65.0 db min effective number of bits (enobs) 11.3 11.2 10.8 db typ 11.2 11.1 10.5 db min signal-to-noise ratio (snr) 70.1 69.7 68.8 db typ 69.0 68.5 67.5 db min total harmonic distortion (thd) C83.4 C82.9 C72.0 db typ C77.5 C75.0 C68.0 db max spurious free dynamic range (sfdr) 86.0 85.7 75.0 db typ 79.0 76.0 69.0 db max full power bandwidth 25 40 60 mhz typ small signal bandwidth 25 40 60 mhz typ aperture delay 1 1 1 ns typ aperture jitter 4 4 4 ps rms typ acquisition to full-scale step 125 43 30 ns typ specifications subject to change without notice. digital specifications parameters symbol units clock input high level input voltage v ih +3.5 v min low level input voltage v il +1.0 v max high level input current (v in = dvdd) i ih 10 m a max low level input current (v in = 0 v) i il 10 m a max input capacitance c in 5 pf typ logic outputs dvdd = 5 v high level output voltage (i oh = 50 m a) v oh +4.5 v min high level output voltage (i oh = 0.5 ma) v oh +2.4 v min low level output voltage (i ol = 1.6 ma) v ol +0.4 v max low level output voltage (i ol = 50 m a) v ol +0.1 v max dvdd = 3 v high level output voltage (i oh = 50 m a) v oh +2.95 v min high level output voltage (i oh = 0.5 ma) v oh +2.80 v min low level output voltage (i ol = 1.6 ma) v ol +0.4 v max low level output voltage (i ol = 50 m a) v ol +0.05 v max output capacitance c out 5 pf typ specifications subject to change without notice. ad9221/ad9223/ad9220 rev. c C3C (avdd = +5 v, dvdd = +5 v, t min to t max unless otherwise noted) (avdd = +5 v, dvdd= +5 v, f sample = max conversion rate, v ref = 1.0 v, vinb = 2.5 v, dc coupled/single- ended input t min to t max unless otherwise noted)
ad9221/ad9223/ad9220 rev. c C4C switching specifications parameters symbol ad9221 ad9223 ad9220 units clock period 1 t c 667 333 100 ns min clock pulsewidth high t ch 300 150 45 ns min clock pulsewidth low t cl 300 150 45 ns min output delay t od 8 8 8 ns min 13 13 13 ns typ 19 19 19 ns max pipeline delay (latency) 3 3 3 clock cycles notes 1 the clock period may be extended to 1 ms without degradation in specified performance @ +25 c. specifications subject to change without notice. (t min to t max with avdd = +5 v, dvdd = +5 v, c l = 20 pf) t cl t ch t c t od data 1 data output input clock analog input s1 s2 s3 s4 figure 1. timing diagram caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although these devices feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings* with respect parameter to min max units avdd avss C0.3 +6.5 v dvdd dvss C0.3 +6.5 v avss dvss C0.3 +0.3 v avdd dvdd C6.5 +6.5 v refcom avss C0.3 +0.3 v clk avss C0.3 avdd + 0.3 v digital outputs dvss C0.3 dvdd + 0.3 v vina, vinb avss C0.3 avdd + 0.3 v vref avss C0.3 avdd + 0.3 v sense avss C0.3 avdd + 0.3 v capb, capt avss C0.3 avdd + 0.3 v junction temperature +150 c storage temperature C65 +150 c lead temperature (10 sec) +300 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may effect device reliability. thermal characteristics thermal resistance 28-lead soic q ja = 71.4 c/w q jc = 23 c/w 28-lead ssop q ja = 63.3 c/w q jc = 23 c/w ordering guide temperature package package model range description options ad9221ar C40 c to +85 c 28-lead soic r-28 ad9223ar C40 c to +85 c 28-lead soic r-28 ad9220ar C40 c to +85 c 28-lead soic r-28 ad9221ars C40 c to +85 c 28-lead ssop rs-28 ad9223ars C40 c to +85 c 28-lead ssop rs-28 ad9220ars C40 c to +85 c 28-lead ssop rs-28 ad9220/ad9221/ad9223soiceb evaluation board ad9220/ad9221/ad9223ssopeb evaluation board warning! esd sensitive device
ad9221/ad9223/ad9220 rev. c C5C zero error the major carry transition should occur for an analog value 1/2 lsb below vina = vinb. zero error is defined as the deviation of the actual transition from that point. gain error the first code transition should occur at an analog value 1/2 lsb above negative full scale. the last transition should occur at an analog value 1 1/2 lsb below the nominal full scale. gain error is the deviation of the actual difference between first and last code transitions and the ideal differ- ence betw een first and last code transitions. temperature drift the temperature drift for zero error and gain error specifies the maximum change from the initial (+25 c) value to the value at t min or t max . power supply rejection the specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. aperture jitter aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the a/d. aperture delay aperture delay is a measure of the sample-and-hold amplifier (sha) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion. signal-to-noise and distortion (s/n+d, sinad) ratio s/n+d is the ratio of the rms value of the measured input sig- nal to the rms sum of all other spectral components below the nyquist frequen cy, including harmonics but excluding dc. the value for s/n+d is expressed in decibels. effective number of bits (enob) for a sine wave, sinad can be expressed in terms of the num- ber of bits. using the following formula, n = ( sinad C 1.76)/6.02 it is possible to get a measure of performance expressed as n , the effective number of bits. thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured sinad. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, excluding the first six harmonics and dc. the value for snr is expressed in decibels. spurious free dynamic range (sfdr) sfdr is the difference in db between the rms amplitude of the input signal and the peak spurious signal. pin connections 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) 28 27 26 25 24 23 22 21 ad9221/ ad9223/ ad9220 clk avss avdd dvss dvdd (lsb) bit 12 bit 11 bit 10 cml vina vinb bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 refcom capb capt bit 3 bit 2 (msb) bit 1 otr vref avdd avss sense pin function descriptions pin number name description 1 clk clock input pin 2 bit 12 least significant data bit (lsb) 3C12 bit n data output bit 13 bit 1 most significant data bit (msb) 14 otr out of range 15, 26 avdd +5 v analog supply 16, 25 avss analog ground 17 sense reference select 18 vref reference i/o 19 refcom reference common 20 capb noise reduction pin 21 capt noise reduction pin 22 cml common-mode level (midsupply) 23 vina analog input pin (+) 24 vinb analog input pin (C) 27 dvss digital ground 28 dvdd +3 v to +5 v digital supply definitions of specification integral nonlinearity (inl) inl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the middle of each particular code to the true straight line. differential nonlinearity (dnl, no missing codes) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. guaranteed no missing codes to 12-bit resolution indicates that all 4096 codes, respectively, must be present over all operating ranges.
ad9221/ad9223/ad9220 rev. c C6C ad9221Ctypical characterization curves 1.0 0.4 ?.6 0 4095 0.8 0.6 0.0 ?.4 0.2 ?.2 ?.8 ?.0 code dnl ?lsbs figure 2. typical dnl frequency ?mhz sinad ?db 80 75 40 0.1 1.0 70 65 45 60 55 50 ?.5db ?.0db ?0.0db figure 5. sinad vs. input frequency (input span = 2.0 v p-p, v cm = 2.5 v) frequency ?mhz thd?db ?0 ?5 ?0 0.1 1.0 ?0 ?5 ?5 ?0 ?5 ?0 ?.5db ?.0db ?0.0db figure 8. thd vs. input frequency (input span = 5.0 v p-p, v cm = 2.5 v) (avdd = +5 v, dvdd = +5 v, f sample = 1.5 msps, t a = +25 8 c) 1.0 0.4 ?.0 0 4095 0.8 0.6 0.0 ?.8 0.2 ?.6 ?.2 ?.4 code inl ?lsbs figure 3. typical inl frequency ?mhz ?0 ?5 ?0 0.1 1.0 ?0 ?5 ?5 ?0 ?5 ?0 ?.5db ?.0db ?0.0db ?5 ?00 thd ?db figure 6. thd vs. input frequency (input span = 2.0 v p-p, v cm = 2.5 v) sample rate ?msps thd ?db ?0 ?5 ?00 0.2 1 2 ?0 ?5 ?5 ?0 ?5 ?0 3 0.3 0.8 5v p-p 2v p-p 0.4 0.6 figure 9. thd vs. sample rate (a in = C0.5 db, f in = 500 khz, v cm = 2.5 v) code hits 121,764 8,180,388 85,895 n? n n+1 figure 4. grounded-input histogram (input span = 2 v p-p) frequency ?mhz sinad ?db 80 75 40 0.1 1.0 70 65 45 60 55 50 ?.5db ?.0db ?0.0db figure 7. sinad vs. input frequency (input span = 5.0 v p-p, v cm = 2.5 v) a in ?dbfs 100 90 30 ?0 ?0 ?0 ?0 70 60 40 50 80 20 snr/sfdr ?db 10 ?0 ?0 0 sfdr snr figure 10. snr/sfdr vs. a in (input amplitude) (f in = 500 khz, input span = 2 v p-p, v cm = 2.5 v)
ad9221/ad9223/ad9220 rev. c C7C ad9223Ctypical characterization curves code 1.0 0.4 ?.0 0 4095 0.8 0.6 0.0 ?.8 0.2 ?.6 ?.2 ?.4 0 inl ?lsbs figure 12. typical inl frequency ?mhz thd ?db ?0 ?5 ?0 0.1 1.0 10.0 ?0 ?5 ?5 ?0 ?5 ?0 ?0.0db ?.0db ?.5db ?5 ?00 figure 15. thd vs. input frequency (input span = 2.0 v p-p, v cm = 2.5 v) sample rate ?msps thd ?db ?0 ?5 ?00 0.4 0.8 4 ?0 ?5 ?5 ?0 ?5 ?0 0.6 1 2 3 5 6 5v p-p 2v p-p figure 18. thd vs. sample rate (a in = C0.5 db, f in = 500 khz, v cm = 2.5 v) (avdd = +5 v, dvdd = +5 v, f sample = 3.0 msps, t a = +25 8 c) code 1.0 0.4 ?.6 0 4095 0.8 0.6 0.0 ?.4 0.2 ?.2 ?.8 ?.0 dnl ?lsbs figure 11. typical dnl frequency ?mhz sinad ?db 80 75 40 0.1 1.0 10.0 70 65 45 60 55 50 ?.5db ?.0db ?0.0db figure 14. si nad vs. input fre quency (input span = 2.0 v p-p, v cm = 2.5 v) frequency ?mhz thd ?db ?0 ?5 ?0 0.1 1.0 10.0 ?0 ?5 ?5 ?0 ?5 ?0 ?0.0db ?.0db ?.5db ?5 ?00 figure 17. thd vs. input fre quency (input span = 5.0 v p-p, v cm = 2.5 v) code hits 96,830 8,123,672 130,323 n? n n+1 figure 13. grounded-input histogram (input span = 2 v p-p) frequency ?mhz sinad ?db 80 75 40 0.1 1.0 10.0 70 65 45 60 55 50 ?.5db ?.0db ?0.0db figure 16. sinad vs. input fre quency (input span = 5.0 v p-p, v cm = 2.5 v) a in ?dbfs 100 90 30 ?0 ?0 0 ?0 70 60 40 50 80 snr/sfdr ?db 20 10 ?0 ?0 ?0 sfdr snr figure 19. snr/sfdr vs. a in (input amplitude) (f in = 1.5 mhz, input span = 2 v p-p, v cm = 2.5 v)
ad9221/ad9223/ad9220 rev. c C8C ad9220Ctypical characterization curves (avdd = +5 v, dvdd = +5 v, f sample = 10 msps, t a = +25 8 c) code 1.0 0.4 ?.6 1 4095 0.8 0.6 0.0 ?.4 0.2 ?.2 ?.8 ?.0 dnl ?lsbs figure 20. typical dnl frequency ?mhz 80 75 40 70 65 45 60 55 50 0.1 1.0 10.0 sinad ?db ?.5db ?db ?0db figure 23. sinad vs. input fre- quency (input span = 2.0 v p-p, v cm = 2.5 v) frequency ?mhz ?0 thd ?db ?5 ?0 0.1 1.0 10.0 ?0 ?5 ?5 ?0 ?5 ?0 ?.0db ?.5db ?0.0db figure 26. thd vs. input frequency (input span = 5.0 v p-p, v cm = 2.5 v) code 1.0 0.4 ?.0 1 4095 0.8 0.6 0.0 ?.8 0.2 ?.6 ?.2 ?.4 inl ?lsbs figure 21. typical inl frequency ?mhz ?0 ?5 ?00 0.5 1.0 10.0 ?0 ?5 ?5 ?0 ?5 ?0 ?0 ?5 thd ?db ?0db ?db ?.5db figure 24. thd vs. input frequency (input span = 2.0 v p-p, v cm = 2.5 v) sample rate ?msps thd ?db ?0 ?5 ?00 110 ?0 ?5 ?5 ?0 ?5 ?0 5v p-p 2v p-p 15 figure 27. thd vs. clock frequency (a in = C0.5 db, f in = 1.0 mhz, v cm = 2.5 v) code hits 134,613 8,123,672 130,323 n? n n+1 figure 22. grounded-input histogram (input span = 2 v p-p) frequency ?mhz sinad ?db 80 75 40 0.1 1.0 10.0 70 65 45 60 55 50 ?.0db ?.5db ?0.0db figure 25. sinad vs. input fre- quency (input span = 5.0 v p-p, v cm = 2.5 v) a in ?dbfs 90 80 20 ?0 ?0 0 ?0 60 50 30 40 70 snr/sfdr ?db 10 ?0 ?0 ?0 sfdr snr figure 28. snr/s fdr vs. a in (input amplitude) (f in = 5.0 mhz, input span = 2 v p-p, v cm = 2.5 v)
ad9221/ad9223/ad9220 rev. c C9C introduction the ad9221/ad9223/ad9220 are members of a high perfor- mance, complete single -supply 12-bit adc product family based on the same cmos pipelined architecture. the product family allows the system designer an upward or downward component selection path based on dynamic performance, sample rate, and power. the analog input range of the ad9221/ad9223/ad9220 is highly flexible allowing for both single-ended or differential inputs of varying amplitudes which can be ac or dc coupled. each device shares the same interface options, pinout and pack- age offering. the ad9221/ad9223/ad9220 utilize a four-stage pipeline architecture with a wideband input sample-and-hold amplifier (sha) implemented on a cost-effective cmos process. each stage of the pipeline, excluding the last stage, consists of a low resolution flash a/d connected to a switched capacitor dac and interstage residue amplifier (mdac). the residue amplifier amplifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each of the stages to facilitate digital correction of flash errors. the last stage simply consists of a flash a/d. the pipeline architecture allows a greater throughput rate at the expense of pipeline delay or latency. this means that while the converter is capable of capturing a new input sample every clock cycle, it actually takes three clock cycles for the conversion to be fully processed and appear at the output. this latency is not a concern in most applications. the digital output, together with the out-of-range indicator (otr), is latched into an output buffer to drive the output pins. the output drivers of the ad9220ars, ad9221 and ad9223 can be configured to interface with +5 v or +3.3 v logic families, while the ad9220ar can only be configured for +5 v logic. the ad9221/ad9223/ad9220 use both edges of the clock in their internal timing circuitry (see figure 1 and specification page for exact timing requirements). the a/d samples the ana- log input on the rising edge of the clock input. during the clock low time (between the falling edge and rising edge of the clock), the input sha is in the sample mode; during the clock high time it is in hold. system disturbances just prior to the rising edge of the clock and/or excessive clock jitter may cause the input sha to acquire the wrong value, and should be minimized. the internal circuitry of both the input sha and individual pipeline stages of each member of the product family are opti- mized for both power dissipation and performance. an inherent tradeoff exists between the input shas dynamic performance and its power dissipation . figures 29 and 30 shows this tradeoff by comparing the full-power bandwidth and settling time of the ad9221/ad9223/ad9220. both figures reveal that higher full-power bandwidths and faster settling times are achieved at the expense of an increase in power dissipation. similarly, a tradeoff exists between the sampling rate and the power dissipated in each stage. as previously stated, the ad9220, ad9221 and ad9223 are similar in most aspects except for the specified sampling rate, power consumption, and dynamic performance. the product family is highly flexible providing several different input ranges and interface options. as a result, many of the application issues and tradeoffs associated with these resulting configurations are also similar. the data sheet is structured such that the designer can make an informed decision in selecting the proper a/d and optimizing its performance to fit the specific application. frequency ?mhz 0 ? ?2 1 100 10 amplitude ?db ? ? ad9221 ad9220 ad9223 figure 29. full-power bandwidth settling time ?ns code 4000 3000 0 0 60 10 20 30 40 50 2000 1000 ad9220 ad9223 ad9221 figure 30. settling time analog input and reference overview figure 31, a simplified model of the ad9221/ad9223/ad9220, highlights the relationship between the analog inputs, vina, vinb, and the reference voltage, vref. like the voltage applied to the top of the resistor ladder in a flash a/d converter, the value vref defines the maximum input voltage to the a/d core . the minimum input voltage to the a/d core is automatically defined to be Cvref. v core vina vinb +v ref Cv ref a/d core 12 ad9221/ad9223/ad9220 figure 31. ad9221/ad9223/ad9220 equivalent functional input circuit
ad9221/ad9223/ad9220 rev. c C10C the addition of a differential input structure gives the user an additional level of flexibility that is not possible with traditional flash converters. the input stage allows the user to easily con- figure the inputs for either single-ended operation or differential operation. the a/ds input structure allows the dc offset of the input signal to be varied independently of the input span of the converter. specifically, the input to the a/d core is the differ- ence of the voltages applied at the vina and vinb input pins. therefore, the equation, v core = vina C vinb (1) defines the output of the differential input stage and provides the input to the a/d core. the voltage, v core , must satisfy the condition, C vref v core vref (2) where vref is the voltage at the vref pin. while an infinite combination of vina and vinb inputs exist that satisfy equation 2, there is an additional limitation placed on the inputs by the power supply voltages of the ad9221/ ad9223/ad9220. the power supplies bound the valid operat- ing range for vina and vinb. the condition, avss C 0.3 v < vina < avdd + 0.3 v (3) avss C 0.3 v < vinb < avdd + 0.3 v where avss is nominally 0 v and avdd is nominally +5 v, defi nes this requirement. thus, the range of valid inputs for vina and vinb is any combination that satisfies both equa- tions 2 and 3. for additional information showing the relationship between vina, vinb, vref and the digital output of the ad9221/ ad9223/ad9220, see table iv. refer to table i and table ii at the end of this section for a summary of both the various analog input and reference configurations . analog input operation figure 32 shows the equivalent analog input of the ad9221/ ad9223/ad9220 which consists of a differential sample-and- hold amplifier (sha). the differential input structure of the sha is highly flexible, allowing the devices to be easily config- ured for either a differential or single-ended input. the dc offset, or common-mode voltage, of the input(s) can be set to accommodate either single-supply or dual supply systems. also, note that the analog inputs, vina and vinb, are interchange- able with the exception that reversing the inputs to the vina and vinb pins results in a polarity inversion. c s q s1 q h1 vina vinb c s q s1 c pin C c par c pin + c par q s2 c h q s2 c h figure 32. ad9221/ad9223/ad9220 simplified input circuit the shas optimum distortion performance for a differential or single-ended input is achieved under the following two condi- tions: (1) the common-mode voltage is centered around mid supply (i.e., avdd/2 or approximately 2.5 v) and (2) the input signal voltage span of the sha is set at its lowest (i.e., 2 v input span). this is due to the sampling switches, q s1 , being cmos switches whose r on resistance is very low but has some signal dependency which causes frequency dependent ac distortion while the sha is in the track mode. the r on resistance of a cmos switch is typically lowest at its midsupply but increases symmetrically as the input signal approaches either avdd or avss. a lower input signal voltage span centered at midsupply reduces the degree of r on modulation. figure 32a compares the ad9221/ad9223/ad9220s thd vs. frequency performance for a 2 v input span with a common- mode voltage of 1 v and 2.5 v. note how each a/d with a common-mode voltage of 1 v exhibits a similar degradation in thd performance at higher frequencies (i.e., beyond 750 khz). similarly, note how the thd performance at lower frequencies becomes less sensitive to the common-mode voltage. as the input frequency approaches dc, the distortion will be domi- nated by static nonlinearities such as inl and dnl. it is important to note that these dc static nonlinearities are inde- pendent of any r on modulation. frequency C mhz C90 0.1 10 1 thd C db C80 C70 C60 C50 ad9221 1v cm ad9220 1v cm ad9223 1v cm ad9223 2.5v cm ad9221 2.5v cm ad9220 2.5v cm figure 32a. ad9221/ad9223/ad9220 thd vs. frequency for v cm = 2.5 v and 1.0 v (a in = C0.5 db, input span = 2.0 v p-p) due to the high degree of symmetry within the sha topology, a significant improvement in distortion performance for differen- tial input signals with frequencies up to and beyond nyquist can be realized. this inherent symmetry provides excellent cancella- tion of both common-mode distortion and noise. also, the required input signal voltage span is reduced by a half which further reduces the degree of r on modulation and its effects on distortion. the optimum noise and dc linearity performance for either differ- ential or single-ended inputs is achieved with the largest input signal voltage span (i.e., 5 v input span) and matched input impedance for vina and vinb. note that only a slight degra- dation in dc linearity performance exists between the 2 v and 5 v input span as specified in the ad9221/ad9223/ad9220 dc specifications.
ad9221/ad9223/ad9220 rev. c C11C referring to figure 32, the differential sha is implemented using a switched-capacitor topology. hence, its input imped- ance and its subsequent effects on the input drive source should be understood to maximize the converters performance. the combination of the pin capacitance, c pin , parasitic capacitance c par, and the sampling capacitance, c s , is typically less than 16 pf. when the sha goes into track mode, the input source must charge or discharge the voltage stored on c s to the new input voltage. this action of charging and discharging c s , averaged over a period of time and for a given sampling fre- quency, f s , makes the input impedance appear to have a benign resistive component. however, if this action is analyzed within a sampling period (i.e., t = 1/f s ), the input impedance is dy- namic and hence certain precautions on the input drive source should be observed. the resistive component to the input impedance can be com- puted by calculating the average charge that gets drawn by c h from the input drive source. it can be shown that if c s is al- lowed to fully charge up to the input voltage before switches q s1 are opened, then the average current into the input is the same as if there were a resistor of 1/(c s f s ) ohms connected between the inputs. this means that the input impedance is inversely proportional to the converters sample rate. since c s is only 4 pf, this resistive component is typically much larger than that of the drive source (i.e., 25 k w at f s = 10 msps). if one considers the shas input impedance over a sampling period, it appears as a dynamic input impedance to the input drive source. when the sha goes into the track mode, the input source should ideally provide the ch arging current through r on of switch q s1 in an exponential manner. the requirement of exponential charging means that the most common input source, an op amp, must exhibit a source impedance that is both low and resistive up to and beyond the sampling frequency. the output impedance of an op amp can be modeled with a series inductor and resistor. when a capacitive load is switched onto the output of the op amp, the output will momentarily drop due to its effective output impedance. as the output re- covers, ringing may occur. to remedy the situation, a series resistor can be inserted between the op amp and the sha input as shown in figure 33. the series resistance helps isolate the op amp from the switched-capacitor load. 10 m f vina vinb sense ad9221/ad9223/ ad9220 0.1 m f r s v cc v ee r s vref refcom figure 33. series resistor isolates switched-capacitor sha input from op amp. matching resistors improve snr performance the optimum size of this resistor is dependent on several factors which include the ad9221/ad9223/ad9220 sampling rate, the selected op amp, and the particular application. in most applications, a 30 w to 50 w resistor is sufficient. however, some applications may require a larger resistor value to reduce the noise bandwidth or possibly limit the fault current in an over- voltage condition. other applications may require a larger resistor value as part of an antialiasing filter. in any case, since the thd performance is dependent on the series resistance and the above mentioned factors, optimizing this resistor value for a given application is encouraged. a slight improvement in snr performance and dc offset performance is achieved by matching the input resistance of vina and vinb. the degree of improvement is dependent on the resistor value and the sampling rate. for series resistor values greater than 100 w , the use of a matching resistor is encouraged. figure 34 shows a plot for thd performance vs. r series for the ad9221/ad9223/ad9220 at their respective sampling rate and nyquist frequency. the nyquist frequency typically repre- sents the worst case scenario for an adc. in this case, a high speed, high performance amplifier (ad8047) was used as the buffer op amp. although not shown, the ad9221/ad9223/ ad9220 exhibits a slight increase in snr (i.e. 1 db to 1.5 db) as the resistance is increased from 0 k w to 2.56 k w due to its bandlimiting effect on wideband noise. conversely, it exhibits slight decrease in snr (i.e., 0.5 db to 2 db) if vina and vinb do not have a matched input resistance. r series C v C45 C55 C85 1 10k 10 thd C db 100 1k C65 C75 ad9220 ad9223 ad9221 figure 34. thd vs. r series (f in = f s /2, a in = C0.5 db, input span = 2 v p-p, v cm = 2.5 v) figure 34 shows that a small r series between 30 w and 50 w provides the optimum thd performance for the ad9220. lower values of r series are acceptable for the ad9223 and ad9221 as their lower sampling rates provide a lon ger transient recovery period for the ad8047. note that op amps with lower bandwidths will typically have a longer transient recovery period and hence require a slightly higher value of r series and/or lower sampling rate to achieve the optimum thd performance. as the value of r series increases, a corresponding increase in distortion is noted. this is due to its interaction with the shas parasitic capacitor, c par, which has a signal dependency. hence, the resulting r-c time constant is signal dependent and conse- quently a source of distortion. the noise or small-signal bandwidth of the ad9221/ad9223/ ad9220 is the same as their full-power bandwidth as shown in
ad9221/ad9223/ad9220 rev. c C12C other comparator controls internal circuitry which will disable the reference amplifier if the sense pin is tied avdd. dis- abling the reference amplifier allows the vref pin to be driven by an external voltage reference. a2 5k v 5k v 5k v 5k v logic disable a2 7.5k v logic 5k v disable a1 1v to a/d ad9221/ad9223/ad9220 capt capb vref sense refcom a1 figure 35. equivalent reference circuit the actual reference voltages used by the internal circuitry of the ad9221/ad9223/ad9220 appear on the capt and capb pins. for proper operation when using the internal or an exter- nal reference, it is necessary to add a capacitor network to de- couple these pins. figure 36 shows the recommended decoupling network. this capacitive network performs the following three functions: (1) along with the reference ampli- fier, a2, it provides a low source impedance over a large fre- quency range to drive the a/d internal circuitry, (2) it provides the necessary compensation for a2, and (3) it bandlimits the noise contribution from the reference. the turn-on time of the reference voltage appearing between capt and capb is ap- proximately 15 ms and should be evaluated in any power- down mode of operation. 0.1 m f 10 m f 0.1 m f 0.1 m f capt capb ad9221/ ad9223/ ad9220 figure 36. r ecommended capt/capb decoupling network the a/ds input span may be varied dynamically by changing the differential reference voltage appearing across capt and capb symmetrically around 2.5 v (i.e., midsupply). to change the reference at speeds beyond the capabilities of a2, it will be necessary to drive capt and capb with two high speed, low noise amplifiers. in this case, both internal am plifiers (i.e., a1 and a2) must be disabled by connecting sense to avdd and vref to refcom and the capacitive decoupling network removed. the external voltages applied to capt and capb must be 2.5 v + input span/4 and 2.5 v C input span/4 respec- tively in which the input span can be varied between 2 v and 5 v. note that those samples within the pipeline a/d during any reference transition will be corrupted and should be discarded. figure 29. for noise sensitive applications, the excessive band- width may be detrimental and the addition of a series resistor and/or shunt capacitor can help limit the wideband noise at the a/ds input by forming a low-pass filter. note, however, that the combination of this series resistance with the equivalent input capacitance of the ad9221/ad9223/ad9220 should be evaluated for those time-domain applications that are sensitive to the input signals absolute settling time. in applications where harmonic distortion is not a primary concern, the series resis- tance may be selected in combination with the shas nominal 16 pf of input capacitance to set the filters 3 db cutoff frequency. a better method of reducing the noise bandwidth, while possi- bly establishing a real pole for an antialiasing filter, is to add some additional shunt capacitance between the input (i.e., vina and/or vinb) and analog ground. since this additional shunt capacitance combines with the equivalent input capaci- tance of the ad9221/ad9223/ad9220, a lower series resis- tance can be selected to establish the filters cutoff frequency while not degrading the distortion performance of the device. the shunt capacitance also acts like a charge reservoir, sinking or sourcing the additional charge required by the hold capacitor, c h , further reducing current transients seen at the op amps output. the effect of this increased capacitive load on the op amp driv- ing the ad9221/ad9223/ad9220 should be evaluated. to optimize performance when noise is the primary consideration, increase the shunt capacitance as much as the transient response of the input signal will allow. increasing the capacitance too much may adversely affect the op amps settling time, frequency response, and distortion performance. reference operation the ad9221/ad9223/ad9220 contain an onboard bandgap reference that provides a pin-strappable option to generate either a 1 v or 2.5 v output. with the addition of two external re sistors, the user can generate reference voltages other than 1 v and 2.5 v. another alternative is to use an external reference for designs requiring enhanced accuracy and/or drift performance. see table ii for a summary of the pin-strapping options for the ad9221/ad9223/ad9220 reference configurations. figure 35 shows a simplified model of the internal voltage refer- ence of the ad9221/ad9223/ad9220. a pin-strappable refer- ence amplifier buffers a 1 v fixed reference. the output from the reference amplifier, a1, appears on the vref pin. the voltage on the vref pin determines the full-scale input span of the a/d. this input span equals, full-scale input span = 2 vref the voltage appearing at the vref pin as well as the state of the internal reference amplifier, a1, are determined by the volt- age appearing at the sense pin. the logic circuitry contains two comparators which monitor the voltage at the sense pin. the comparator with the lowest set point (approximately 0.3 v) controls the position of the switch within the feedback path of a1. if the sense pin is tied to refcom, the switch is con- nected to the internal resistor network thus providing a vref of 2.5 v. if the sense pin is tied to the vref pin via a short or resistor, the switch is connected to the sense pin. a short will provide a vref of 1.0 v while an external resistor network will provide an alternative vref between 1.0 v and 2.5 v. the
ad9221/ad9223/ad9220 rev. c C13C table i. analog input configuration summary input input input range (v) figure connection coupling span (v) vina 1 vinb 1 # comments single-ended dc 2 0 to 2 1 39, 40 best for stepped input response applications, suboptimum thd and noise performance, requires 5 v op amp. 2 vref 0 to vref 39, 40 same as above but with improved noise performance due to 2 vref increase in dynamic range. headroom/settling time require- ments of 5 v op amp should be evaluated. 5 0 to 5 2.5 39, 40 optimum noise performance, excellent thd performance, requires op amp with vcc > +5 v due to headroom issue. 2 vref 2.5 C vref 2.5 50 optimum thd performance with vref = 1, noise to performance improves while thd performance degrades as 2.5 + vref vref increases to 2.5 v. single supply operation (i.e., +5 v) for many op amps. single-ended ac 2 or 0 to 1 or 1 or vref 41 suboptimum ac performance due to input common-mode 2 vref 0 to 2 vref level not biased at optimum midsupply level (i.e., 2.5 v). 5 0 to 5 2.5 41 optimum noise performance, excellent thd performance, ability to use 5 v op amp. 2 vref 2.5 C vref 2.5 42 flexible input range, optimum thd performance with to vref = 1. noise performance improves while thd perfor- 2.5 + vref mance degrades as vref increases to 2.5 v. ability to use +5 v or 5 v op amp. differential ac 2 2 to 3 3 to 2 45 optimum full-scale thd and sfdr performance well be- (via transformer) yond the a/ds nyquist frequency. preferred mode for under- sampling applications. 2 vref 2.5 C vref/2 2.5 + vref/2 45 same as 2 v to 3 v input range with the exception that full-scale to to thd and sfdr performance can be traded off for better noise 2.5 + vref/2 2.5 C vref/2 performance. refer to discussion in ac coupling and interface issue section and simple ac interface section. 5 1.75 to 3.25 3.25 to 1.75 45 optimum noise performance. also, the optimum thd and sfdr performance for less than full-scale signals (i.e., C6 dbfs). refer to discussion in ac coupling and interface issue section and simple ac interface section. note 1 vina and vinb can be interchanged if signal inversion is required. table ii. reference configuration summary reference input span (vinaCvinb) operating mode (v p-p) required vref (v) connect to internal 2 1 sense vref internal 5 2.5 sense refcom internal 2 span 5 and 1 vref 2.5 and r1 vref and sense span = 2 vref vref = (1 + r1/r2) r2 sense and refcom external 2 span 51 vref 2.5 sense avdd (nondynamic) vref ext. ref. external 2 span 5 capt and capb sense avdd (dynamic) externally driven vref refcom ext. ref. capt ext. ref. capb
ad9221/ad9223/ad9220 rev. c C14C amps which may otherwise have been constrained by headroom limitations, (3) differential operation minimizes even-order harmonic products, and (4) differential operation offers noise immunity based on the devices common-mode rejection. fig- ure 37 depicts the common-mode rejection of the three devices. as is typical of most cmos devices, exceeding the supply limits will turn on internal parasitic diodes resulting in transient currents within the device. figure 38 shows a simple means of clamping an ac or dc coupled single-ended input with the addi- tion of two series resistors and two diodes. an optional capaci- tor is shown for ac coupled applications. note that a larger series resistor could be used to limit the fault current through d1 and d2 but should be evaluated since it can cause a degra- dation in overall performance. a similar clamping circuit could also be used for each input if a differential input signal is being applied. avdd ad9221/ ad9223/ ad9220 r s1 30 v v cc v ee optional ac coupling capacitor d2 1n4148 d1 1n4148 r s2 20 v figure 38. simple clamping circuit single-ended mode of operation the ad9221/ad9223/ad9220 can be configured for single- ended operation using dc or ac coupling. in either case, the input of the a/d must be driven from an operational amplifier that will not degrade the a/ds performance. because the a/d operates from a single-supply, it will be necessary to level-shift ground-based bipolar signals to comply with its input require- ments. both dc and ac coupling provide this necessary func- tion, but each method results in different interface issues which may influence the system design and performance. dc coupling and interface issues many applications require the analog input signal to be dc coupled to the ad9221/ad9223/ad9220. an operational amplifier can be configured to rescale and level shift the input signal so that it is compatible with the selected input range of the a/d. the input range to the a/d should be selected on the basis of system performance objectives as well as the analog power supply availability since this will place certain constraints on the op amp selection. many of the new high performance op amps are specified for only 5 v operation and have limited input/output swing capa bilities. hence, the selected input range of the ad9221/ ad9223/ad9220 should be sensitive to the headroom require- ments of the particular op amp to prevent clipping of the sig- nal. also, since the output of a dual supply amplifier can swing below C0.3 v, clamping its output should be considered in some applications. in some applications, it may be advantageous to use an op amp specified for single supply +5 v operation since it will inher- ently limit its output swing to within the power supply rails. an amplifier like the ad8041, ad8011, and ad817 are useful for this purpose. r ail-to-rail output amplifiers such as the ad8041 allow the ad9221/ad9223/ad9220 to be configured for larger input spans which improves the noise performance. driving the analog inputs introduction the ad9221/ad9223/ad9220 has a highly flexible input struc- ture allowing it to interface with single-ended or differential input interface circuitry. the applications shown in sections driving the analog inputs and reference configurations, along with the information presented in input and reference over- view of this data sheet, give examples of both single-ended and differential operation. refer to tables i and ii for a list of the different possible input and reference configurations and their associated figures in the data sheet. the optimum mode of operation, analog input range, and asso- ciated interface circuitry will be determined by the particular applications performance requirements as well as power supply options. for example, a dc coupled single-ended input would be appropriate for most data acquisition and imaging applica- tions. also, many communication applications which require a dc coupled input for proper demodulation can take advantage of the ex cellent single-ended distortion performance of the ad9221/ ad9223/ad9220. the input span should be configured such that the systems performance objectives and the headroom requirements of the driving op amp are simultaneously met. alternatively, the differential mode of operation with a trans- former coupled input provides the best thd and sfdr perfor- mance over a wide frequency range. this mode of operation should be considered for the most demanding spectral-based applications which allow ac coupling (e.g., direct if to digital conversion). single-ended operation requires that vina be ac or dc coupled to the input signal source while vinb of the ad9221/ad9223/ ad9220 be biased to the appropriate voltage corresponding to a midscale code transition. note that signal inversion may be easily accomplished by transposing vina and vinb. the rated specifications for the ad9221/ad9223/ad9220 are characterized using single-ended circuitry with input spans of 5 v and 2 v as well as vinb = 2.5 v . differential operation requires that vina and vinb be simulta- neously driven with two equal signals that are in and out of phase versions of the input signal. differential operation of the ad9221/ad9223/ad9220 offers the following benefits: (1) signal swings are smaller and therefore linearity requirements placed on the input signal source may be easier to achieve, (2) signal swings are smaller and therefore may allow the use of op frequency?mhz 20 70 90 0.1 100 1 cmr ?db 10 80 40 60 50 30 ad9221 ad9223 ad9220 figure 37. ad9221/ad9223/ad9220 input cmr vs. input frequency
ad9221/ad9223/ad9220 rev. c C15C if the application requires the largest input span (i.e., 0 v to 5 v) of the ad9221/ad9223/ad9220, the op amp will require larger supplies to drive it. various high speed amplifiers in the op amp selection guide of this data sheet can be selected to accommodate a wide range of supply options. once again, clamping the output of the amplifier should be considered for these applications. two dc coupled op amp circuits using a noninverting and invert- ing topology are discussed below. although not shown, the noninverting and inverting topologies can be easily configured as part of an anti aliasing filter by using a sallen-key or m ultiple- feedback topology, respectively. an additional r-c network can be inserted between the op amps output and the ad9221/ ad9223/ad9220 input to provide a real pole. simple op amp buffer in the simplest case, the input signal to the ad9221/ad9223/ ad9220 will already be biased at levels in accordance with the selected input range. it is simply necessary to provide an ad- equately low source impedance for the vina and vinb analog input pins of the a/d. figure 39 shows the recommended configuration for a single-ended drive using an op amp. in this case, the op amp is shown in a noninverting unity gain configu- ration driving the vina pin. the internal reference drives the vinb pin. note that the addition of a small series resistor of 30 w to 50 w connected to vina and vinb will be beneficial in nearly all cases. refer to analog input operation section for a discussion on resistor selection. figure 39 shows the proper connection for a 0 v to 5 v input range. alternative single- ended input ranges of 0 v to 2 vref can also be realized with the proper configuration of vref (refer to the using the internal reference section). 10 m f vina vinb sense ad9221/ ad9223/ ad9220 0.1 m f r s +v Cv r s vref 5v 0v 2.5v u1 figure 39. single-ended ad9221/ad9223/ad9220 op amp drive circuit op amp with dc level shifting figure 40 shows a dc-coupled level shifting circuit employing an op amp, a1, to sum the input signal with the desired dc offset. configuring the op amp in the inverting mode with the given resistor values results in an ac signal gain of C1. if the signal inversion is undesirable, interchange the vina and vinb connections to reestablish the original signal polarity. the dc voltage at vref sets the common-m ode voltage of the ad9221/ad9223/ad9220. for example, when vref = 2.5 v, the output level from the op amp will also be centered around 2.5 v. the use of ratio matched, thin-film resistor networks will minimize gain and offset errors. also, an optional pull-up resistor, r p , may be used to reduce the output load on vref to 1 ma. 0v dc +vref Cvref vina vinb 0.1 m f 500 v * 0.1 m f 500 v * 7 1 2 3 4 5 a1 6 nc nc +v cc 500 v * r s vref 500 v * r s r p ** avdd *optional resistor network-ohmtek orna500d **optional pull-up resistor when using internal reference ad9221/ ad9223/ ad9220 figure 40. si ngle-ended input with dc-coupled level shift ac coupling and interface issues for applications where ac coupling is appropriate, the op amps output can be easily level shifted to the common-mode voltage, v cm , of the ad9221/ad9223/ad9220 via a coupling capaci- tor. this has the advantage of allowing the op amps common- mode level to be symmetrically biased to its midsupply level (i.e. (v cc + v ee )/2). op amps which operate symmetrically with respect to their power supplies typically provide the best ac performance as well as greatest input/output span. hence, various high speed/performance amplifiers which are restricted to +5 v/C5 v operation and/or specified for +5 v single-supply operation can be easily configured for the 5 v or 2 v input span of the ad9221/ad9223/ad9220. the best ac distortion per- formance is achieved when the a/d is configured for a 2 v input span and common-mode voltage of 2.5 v. note that differential transformer coupling, which is another form of ac coupling, should be considered for optimum ac performance. simple ac interface figure 41 shows a typical example of an ac-coupled, single- ended configuration. the bias voltage shifts the bipolar, ground-referenced input signal to approximately vref. the value for c1 and c2 will depend on the size of the resistor, r. the capacitors, c1 and c2, are typically a 0.1 m f ceramic and 10 m f tantalum capacitor in parallel to achieve a low cutoff frequency while main taining a low impedance over a wide fre- quency range. the com bination of the capacitor and the resistor form a high-pass filter with a high-pass C3 db frequency deter- mined by the equation, f C3 db = 1/(2 p r ( c 1 + c 2)) the low impedance vref voltage source biases both the vinb input and provides the bias voltage for the vina input. figure 41 shows the vref configured for 2.5 v thus the input range c2 vina vinb sense c1 r +5v C5v r s vref +vref 0v Cvref v in c2 c1 r s ad9221/ ad9223/ ad9220 figure 41. ac-coupled input of the a/d is 0 v to 5 v. other input ranges could be selected by changing vref but the a/ds distortion performance will
ad9221/ad9223/ad9220 rev. c C16C degrade slightly as the input common-mode voltage deviates from its optimum level of 2.5 v. alternative ac interface figure 42 shows a flexible ac coupled circuit which can be con- figured for different input spans. since the common-mode voltage of vina and vinb are biased to midsupply indepen- dent of vref, vref can be pin-strapped or reconfigured to achieve input spans between 2 v and 5 v p-p. the ad9221/ ad9223/ad9220s cmrr along with the symmetrical coupling r-c networks will reject both power supply variations and noise. the resistors, r, establish the common-mode voltage. they may have a high value (e.g., 5 k w ) to minimize power consumption and establish a low cutoff frequency. the capacitors, c1 and c2, are typically a 0.1 m f ceramic and 10 m f tantalum capacitor in parallel to achieve a low cutoff frequency while maintaining a low impedance over a wide frequency range. r s isolates the buffer amplifier from the a/d input. the optimum performance is achieved when vina and vinb are driven via ?immetrical networks. the f C3 db point can be approximated by the equation, f C3 db = 1/(2 p r /2 ( c 1 + c 2)) c2 vina vinb c1 r +5v C5v r s v in c1 c2 r r s +5v r r +5v ad9221/ ad9223/ ad9220 figure 42. ac-coupled input-flexible input span, v cm = 2 v op amp selection guide op amp selection for the ad9221/ad9223/ad9220 is highly dependent on a particular application. in general, the perfor- mance requirements of any given application can be character- ized by either time domain or frequency domain parameters. in either case, one should carefully select an op amp which pre- serves the performance of the a/d. this task becomes challeng- ing when one considers the ad9221/ad9223/ad9220s high performance capabilities coupled with other extraneous system level requirements such as power consumption and cost. the ability to select the optimal op amp may be further compli- cated by either limited power supply availability and/or limited acceptable supplies for a desi red op amp. newer, high performance op amps typically have i nput and output range limitations in accordance with their lower supply voltages. as a result, some op amps will be more appropriate in systems where ac-coupling is allowable. when dc-coupling is required, op amps without headroom constraints such as rail-to-rail op amps or ones where larger supplies can be used should be considered. the following section describes some op amps currently available from analog devices. the system designer is always encouraged to contact the factory or local sales office to be updated on analog devices latest amplifier product offerings. highlights of the areas where the op amps excel and where they may limit the performance of the ad9221/ad9223/ad9220 is also included. ad817: 50 mhz unity gbw, 70 ns settling to 0.01%, +5 v to 15 v supplies best applications: sample rates < 7 msps, low- noise, 5 v p-p input range limits: thd above 100 khz ad826: dual version of ad817 best applications: differential and/or low imped- ance input drivers, low noise limits: thd above 100 khz ad818: 130 mhz @ g = +2 bw, 80 ns settling to 0.01%, +5 v to 15 v supplies best applications: sample r ates < 7 msps, low noise, 5 v p-p input ran ge, gains 3 +2 limits: thd above 100 khz ad828: dual version of ad818 best applications: differential and/or low impedance input drivers, low noise, gains 3 +2 limits: thd above 100 khz ad812: dual, 145 mhz unity gbw, single-supply cur- rent feedback, +5 v to 15 v supplies best applications: differential and/or low imped- ance input drivers, sample rates < 7 msps limits: thd above 1 mhz ad8011: f C3 db = 300 mhz, +5 v or 5 v supplies, current feedback best applications: single-supply, ac/dc-coupled, good ac specs, low noise, low power (5 mw) limits: thd above 5 mhz, usable input/output range ad8013: triple, f C3 db = 230 mhz, +5 v or 5 v supplies, current feedback, disable function best applications: 3:1 multiplexer, good ac specs limits: thd above 5 mhz, input range ad9631: 220 mhz unity gbw, 16 ns settling to 0.01%, 5 v supplies best applications: best ac specs, low noise, ac- coupled limits: usable input/output range, power consumption ad8047: 130 mhz unity gbw, 30 ns settling to 0.01%, 5 v supplies best applications: good ac specs, low noise, ac-coupled limits: thd > 5 mhz, usable input range ad8041: rail-to-rail, 160 mhz unity gbw, 55 ns settling to 0.01%, +5 v supply, 26 mw best applications: low power, single-supply sys- tems, dc-coupled, large input range limits: noise with 2 v input range ad8042: dual ad8041 best applications: differential and/or low imped- ance input drivers limits: noise with 2 v input range
ad9221/ad9223/ad9220 rev. c C17C differential mode of operation since not all applications have a signal preconditioned for differ- ential operation, there is often a need to perform a single-ended- to-differential conversion. in systems which do not need to be dc coupled, an rf transformer with a center tap is the best method to generate differential inputs for the ad9221/ad9223/ ad9220. it provides all the benefits of operating the a/d in the differential mode without contributing additional noise or dis- tortion. an rf transformer also has the added benefit of provid- ing electrical isolation between the signal source and the a/d. note that although a single-ended-to-differential op amp topol- ogy would allow dc coupling of the input signal, no significant improvement in thd performance was realized when compared to the dc single-ended mode of operation up to the ad9221/ ad9223/ad9220s nyquist frequency (i.e., f in < f s /2). also, the additional op amp required in the topology tends to in- creases the total system noise, power consumption, and cost. hence, a single-ended mode of operation is recommended for most applications requiring dc coupling. a dramatic improvement in thd and sfdr performance can be realized by operating the ad9221/ad9223/ad9220 in the differential mode using a transformer. figure 43 shows a plot of thd vs. input frequency for the differential transformer coupled circuit for each a/d while figure 44 shows a plot of sfdr vs. input frequency. both figures demonstrate the enhance- ment in spectral performance for the differential-mode of opera- tion. the performance enhancement between the differential and single-ended mode is most noteworthy as the input frequency approaches and goes beyond the nyquist frequency (i.e., f in > f s /2) corresponding to the particular a/d. the figures are also helpful in determining the appropriate a/d for direct if-down conversion or undersampling applications. refer to analog devices application notes an-301 and an-302 for an informative discussion on undersampling. one should select the a/d that meets or exceeds the distortion performance requirements measured over the required frequency passband. for example, the ad9220 achieves the best distortion perfor- mance over an extended frequency range as a result of its greater full-power bandwidth and thus would represent the best selec- tion for an if undersampling application at 21.4 mhz. refer to the applications section of this data sheet for more detailed information and characterization of this particular application. thd ?db frequency ?mhz ?0 ?0 ?0 1 100 10 ?0 ?0 ad9221 ad9223 ad9220 figure 43. ad9221/ad9223/ad9220 thd vs. input fre- quency (v cm = 2.5 v, 2 v p-p input span, a in = C0.5 db) frequency ?mhz ?5 ?5 1 100 10 sfdr ?db ?5 ?5 ?5 ad9221 ad9223 ad9220 figure 44. ad9221/ad9223/ad9220 sfdr vs. input fre- quency (v cm = 2.5 v, 2 v p-p input span, a in = C0.5 db) figure 45 shows the schematic of the suggested transformer circuit. the circuit uses a minicircuits rf transformer, model #t4-6t, which has an impedance ratio of four (turns ratio of 2). the schematic assumes that the signal source has a 50 w source impedance. the 1:4 impedance ratio requires the 200 w secondary termination for optimum power transfer and vswr. the center tap of the transformer provides a convenient means of level shifting the input signal to a desired common-mode voltage. optimum performance can be realized when the center tap is tied to cml of the ad9221/ad9223/ad9220 which is the common-mode bias level of the internal sha. vina vinb ad9221/ ad9223/ ad9220 200 v 49.9 v r s 33 v cml c s 15pf mini circuits t4-1 0.1 m f r s 33 v c s 15pf figure 45. transformer coupled input transformers with other turns ratios may also be selected to optimize the performance of a given application. for example, a given input signal source or amplifier may realize an improve- ment in distortion performance at reduced output power levels and signal swings. hence, selecting a transformer with a higher impedance ratio (e.g., minicircuits t16-6t with a 1:16 imped- ance ratio) effectively steps up the signal level thus further reducing the driving requirements of the signal source. referring to figure 45, a series resistors, r s , and shunt capaci- tor, c s , were inserted between the ad9221/ad9223/ad9220 and the secondary of the transformer. the values of 33 w and 15 pf were selected to specifically optimize both the thd and snr performance of the a/d. r s and c s help provide some isolation from transients at the a/d inputs reflected back through the primary of the transformer. the ad9221/ad9223/ad9220 can be easily configured for either a 2 v p-p input span or 5.0 v p-p input span by setting the internal reference (see table ii). other input spans can be realized with two external gain setting resistors as shown in figure 49 of this data sheet. figure 46 demonstrates how both spans of the ad9220 achieve the high degree of linearity and
ad9221/ad9223/ad9220 rev. c C18C sfdr over a wide range of amplitudes required by the most demanding communication applications. similar performance is achievable with the ad9221 and ad9223 at their correspond- ing nyquist frequency. input amplitude C dbfs 90 20 C50 0 snr/sfdr C db C40 C30 C20 C10 80 70 30 60 50 40 snr C 2.0v p-p snr C 5.0v p-p sfdr C 5.0v p-p sfdr C 2.0v p-p figure 46. ad9220 sfdr, snr vs. input amplitude (f in = 5 mhz, f clk = 10 msps, v cm = 2.5 v, differential) figure 46 also reveals a noteworthy difference in the sfdr and snr performance of the ad9220 between the 2 v p-p and 5 v p-p input span options. first, the snr performance improves by 2 db with a 5.0 v p-p input span due to the increase in dy- namic range. second, the sfdr performance of the ad9220 will improve for input signals below approximately C6.0 dbfs. a 3 db to 5 db improvement was typically realized for input signal levels between C6.0 dbfs and C36 dbfs. this improve- ment in snr and sfdr for a 5.0 v p-p span may be advanta- geous for communication systems that have additional margin or headroom to minimize clipping of the adc. reference configurations the figures associated with this section on internal and external reference operation do not show recommended matching series resistors for vina and vinb for the purpose of simplicity. please refer to section driving the analog inputs, introduction for a discussion of this topic. also, the figures do not show the decoupling network asso- ciated with the capt and capb pins. please refer to the section ref- erence o peration for a discussion of the internal reference circuitry and the recommended decoupling network shown in figure 36. using the internal reference single-ended input with 0 to 2 3 vref range figure 47 shows how to connect the ad9221/ad9223/ad9220 for a 0 v to 2 v or 0 v to 5 v input range via pin strapping the sense pin. an intermediate input range of 0 to 2 vref can be established using the resistor programmable configuration in figure 49 and connecting vref to vinb. in either case, both the common-mode voltage and input span are directly dependent on the value of vref. more specifically, the common-mode voltage is equal to vref while the input span is equal to 2 vref. thus, the valid input range extends from 0 to 2 vref. when vina is 0 v, the digital output will be 000 hex; when vina is 3 2 vref, the digital output will be fff hex. shorting the vref pin directly to the sense pin places the internal reference amplifier in unity-gain mode and the resultant vref output is 1 v. therefore, the valid input range is 0 v to 2 v. however, shorting the sense pin directly to the refcom pin configures the internal reference amplifier for a gain of 2.5 and the resultant vref output is 2.5 v. thus, the valid input range becomes 0 v to 5 v. the vref pin should be bypassed to the refcom pin with a 10 m f tantalum capacitor in parallel with a low-inductance 0.1 m f ceramic capacitor. 10 m f vina vref 0.1 m f vinb 2 3 vref 0v short for 0v to 2v input span sense short for 0v to 5v input span refcom ad9221/ ad9223/ ad9220 figure 47. internal reference2 v p-p input span, v cm = 1 v, or 5 v p-p input span, v cm = 2.5 v single-ended or differential input, v cm = 2.5 v figure 48 shows the single-ended configuration that gives the best dynamic performance (sinad, sfdr). to optimize dynamic specifications, center the common-mode voltage of the analog input at approximately by 2.5 v by connecting vinb to a low-impedance 2.5 v source. as described above, shorting the vref pin directly to the sense pin results in a 1 v refer- ence voltage and a 2 v p-p input span. the valid range for input signals is 1.5 v to 3.5 v. the vref pin should be by- passed to the refcom pin with a 10 m f tantalum capacitor in parallel with a low-inductance 0.1 m f ceramic capacitor. this reference configuration could also be used for a differential input in which vina and vinb are driven via a transformer as shown in figure 45. in this case, the common-mode voltage, v cm , is set at midsupply by connecting the transformers center tap to cml of the ad9221/ad9223/ad9220. vref can be configured for 1 v or 2.5 v by connecting sense to either vref or refcom respectively. note that the valid input range for each of the differential input is one half of the single- ended input and thus becomes v cm C vref/2 to v cm + vref/2. 1v 0.1 m f 10 m f vina vinb vref sense refcom 3.5v 1.5v 2.5v ad9221/ ad9223/ ad9220 figure 48. internal reference2 v p-p input span, v cm = 2.5 v resistor programmable reference figure 49 shows an example of how to generate a reference voltage other than 1 v or 2.5 v with the addition of two exter- nal resistors and a bypass capacitor. use the equation, vref = 1 v (1 + r 1/ r 2), to determine appropriate values for r 1 and r 2. these resistors should be in the 2 k w to 100 k w range. for the example shown, r1 equals 2.5 k w and r2 equals 5 k w . from the equation above, the resultant reference voltage on the vref pin is
ad9221/ad9223/ad9220 rev. c C19C 1.5 v. this sets the input span to be 3 v p-p. to assure stabil- ity, place a 0.1 m f ceramic capacitor in parallel with r1. the common-mode voltage can be set to vref by connecting vinb to vref to provide an input span of 0 to 2 vref. alternatively, the common-mode voltage can be set to vref by connecting vinb to a low impedance 2.5 v source. for the exam ple shown, the valid input single range for vina is 1 v to 4 v since vinb is set to an external, low impedance 2.5 v source. the vref pin should be bypassed to the refcom pin with a 10 m f tantalum capacitor in parallel with a low induc- tance 0.1 m f ceramic capacitor. 1.5v c1 0.1 m f 10 m f vina vinb vref sense refcom ad9220 4v 1v 2.5v r1 2.5k v r2 5k v 0.1 m f figure 49. resistor programmable reference3 v p-p input span, v cm = 2.5 v using an external reference using an external reference may enhance the dc performance of the ad9221/ad9223/ad9220 by improving drift and accuracy. figures 50 through 52 show examples of how to use an external reference with the a/d. table iii is a list of suitable voltage references from analog devices. to use an external reference, the user must disable the internal reference amplifier and drive the vref pin. connecting the sense pin to avdd disables the internal reference amplifier. table iii. suitable voltage references initial operating output drift accuracy current voltage (ppm/ 8 c) % (max) ( m a) internal 1.00 26 1.4 n/a ad589 1.235 10C100 1.2C2.8 50 ad1580 1.225 50C100 0.08C0.8 50 ref191 2.048 5C25 0.1C0.5 45 internal 2.50 26 1.4 n/a ref192 2.50 5C25 0.08C0.4 45 ref43 2.50 10C25 0.06C0.1 600 ad780 2.50 3C7 0.04C0.2 1000 the ad9221/ad9223/ad9220 contains an internal reference buffer, a2 (see figure 35), that simplifies the drive requirements of an external reference. the external reference must be able to drive a ? 5 k w ( 20%) load. note that the bandwidth of the ref- erence buffer is deliberately left small to minimize the reference noise contribution. as a result, it is not possible to change the reference voltage rapidly in this mode without the removal of the capt/capb decoupling network. variable input span with v cm = 2.5 v figure 50 shows an example of the ad9221/ad9223/ad9220 configured for an input span of 2 vref centered at 2.5 v. an external 2.5 v reference drives the vinb pin thus setting the common-mode voltage at 2.5 v. the input span can be inde- pendently set by a voltage divider consisting of r1 and r2 which generates the vref signal. a1 buffers this resistor net- work and drives vref. choose this op amp based on accuracy requirements. it is essential that a minimum of a 10 m f capaci- tor in parallel with a 0.1 m f low inductance ceramic capacitor decouple the reference output to ground. 2.5v+vref 2.5vCvref 2.5v +5v 0.1 m f 22 m f vina vinb vref sense +5v r2 0.1 m f a1 r1 0.1 m f 2.5v ref ad9221/ ad9223/ ad9220 figure 50. external referencev cm = 2.5 v (2.5 v on vinb, resistor divider to make vref) single-ended input with 0 to 2 3 vref range figure 51 shows an example of an external reference driving both vinb and vref. in this case, both the common mode voltage and input span are directly dependent on the value of vref. more specifically, the common mode voltage is equal to vref while the input span is equal to 2 vref. thus, the valid input range extends from 0 to 2 vref. for example, if the ref-191, a 2.048 external reference was selected, the valid input range extends from 0 to 4.096 v. in this case, 1 lsb of the ad9221/ad9223/ad9220 corresponds to 1 mv. it is es- sential that a minimum of a 10 m f capacitor in parallel with a 0.1 m f low inductance ceramic capacitor decouple the reference output to ground. 2 3 ref 0v +5v 10 m f vina vinb vref sense ad9221/ ad9223/ ad9220 +5v 0.1 m f vref 0.1 m f 0.1 m f figure 51. input range = 0 v to 2 vref low cost/power reference the external reference circuit shown in figure 52 uses a low cost 1.225 v external reference (e.g., ad580 or ad1580) along with an op amp and transistor. the 2n2222 transistor acts in conjunction with 1/2 of an op282 to provide a very low imped- ance drive for vinb. the selected op amp need not be a high speed op amp and may be selected based on cost, power and accuracy.
ad9221/ad9223/ad9220 rev. c C20C table v. out-of-range truth table otr msb analog input is 0 0 in range 0 1 in range 1 0 underrange 1 1 overrange over = ? under = ? msb otr msb figure 54. overrange or underrange logic digital output driver considerations (dvdd) the ad9221, ad9223 and ad9220ars output drivers can be configured to interface with +5 v or 3.3 v logic families by setting dvdd to +5 v or 3.3 v respectively. however, the ad9220ar can only be configured to interface with +5 v logic families. the ad9221/ad9223/ad9220 ou tput drivers are sized to provide sufficient output current to drive a wide variety of logic families. however, large drive currents tend to cause glitches on the supplies and may affect si nad performance. applications requiring the ad9221/ad9223/ad9220 to drive large capaci- tive loads or large fanout may require additional decoupling capacitors on dvdd. in extreme cases, external buffers or latches may be required. clock input and considerations the ad9221/ad9223/ad9220 internal timing uses the two edges of the clock input to generate a variety of internal timing signals. the clock input must meet or exceed the minimum specified pulsewidth high and low (t ch and t cl ) specifications for the given a/d as defined in the switching specifications at the beginning of the data sheet to meet the rated performance specifications. for example, the clock input to the ad9220 operating at 10 msps may have a duty cycle between 45% to 55% to meet this timing requirement since the minimum s pecified t ch and t cl is 45 ns. for clock rates below 10 msps, the duty cycle may deviate from this range to the extent that both t ch and t cl are satisfied. all high speed high resolution a/ds are sensitive to the quality of the clock input. the degradation in snr at a given full-scale input frequency (f in ) due to only aperture jitter (t a ) can be calculated with the following equation: snr = 20 log 10 [1/2 p f in t a ] in the equation, the rms aperture jitter, t a , represents the root- sum square of all the jitter sources which include the clock in- put, analog input signal, and a/d aperture jitter specification. for example, if a 5 mhz full-scale sine wave is sampled by an a/d with a total rms jitter of 15 ps, the snr performance of the a/d will be limited to 66.5 db. undersampling applications are particularly sensitive to jitter. the clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the ad9221/ad9223/ad9220. as such, supplies for clock drivers should be separated from the a/d output driver supplies to avoid modulating the clock signal with digital noise. low jitter crystal controlled oscillators make the best clock sources. if the 3.75v 1.25v +5v 10 m f vina vinb vref sense ad9221/ ad9223/ ad9220 +5v 0.1 m f 316 v 1k v 0.1 m f 1/2 op282 10 m f 0.1 m f 7.5k v ad1580 1k v 1k v 820 v +5v 2n2222 1.225v figure 52. external reference using the ad1580 and low impedance buffer digital inputs and outputs digital outputs the ad9221/ad9223/ad9220 output data is presented in positive true straight binary for all input ranges. table iv indi- cates the output data formats for various input ranges regardless of the selected input range. a twos complement output data format can be created by inverting the msb. table iv. output data format i nput (v) condition (v) digital output otr vina Cvinb < C vref 0000 0000 0000 1 vina Cvinb = C vref 0000 0000 0000 0 vina Cvinb = 0 1000 0000 0000 0 vina Cvinb = + vref C 1 lsb 1111 1111 1111 0 vina Cvinb 3 + vref 1111 1111 1111 1 1111 1111 1111 1111 1111 1111 1111 1111 1110 otr ?s +fs ?s+1/2 lsb +fs ?/2 lsb ?s ?/2 lsb +fs ? 1/2 lsb 0000 0000 0001 0000 0000 0000 0000 0000 0000 1 0 0 0 0 1 otr data outputs figure 53. output data format out of range (otr) an out-of-range condition exists when the analog input voltage is beyond the input range of the converter. otr is a digital output that is updated along with the data output corresponding to the particular sampled analog input voltage. hence, otr has the same pipeline delay (latency) as the digital data. it is low when the analog input voltage is within the analog input range. it is high when the analog input voltage exceeds the input range as shown in figure 53. otr will remain high until the analog input returns within the input range and another conver- sion is completed. by logical anding otr with the msb and its com plement, overrange high or underrange low condi- tions can be detected. table v is a truth table for the over/ underrange circuit in figure 54 which uses nand gates. sys- tems requiring programmable gain conditioning of the ad9221/ ad9223/ad9220 input signal can immediately detect an out- of-range condition, thus eliminating gain selection iterations. also, otr can be used for digital offset and gain calibration.
ad9221/ad9223/ad9220 rev. c C21C grounding and decoupling analog and digital grounding proper grounding is essential in any high speed, high resolution system. multilayer printed circuit boards (pcbs) are recom- mended to provide optimal grounding and power schemes. the use of ground and power planes offers distinct advantages: 1. the minimization of the loop area encompassed by a signal and its return path. 2. the minimization of the impedance associated with ground and power paths. 3. the inherent distributed capacitor formed by the power plane, pcb insulation, and ground plane. these characteristics result in both a reduction of electro- magnetic interference (emi) and an overall improvem ent in performance. it is important to design a layout that prevents noise from coupling onto the input signal. digital signals should not be run in paral- lel with input signal traces and should be routed away from the input circuitry. while the ad9221/ad9223/ad9220 features separate analog and digital ground pins, it should be treated as an analog component. the avss and dvss pins must be joined together directly under the ad9221/ad9223/ad9220 . a solid ground plane under the a/d is acceptable if the power and ground return currents are managed carefully. alternatively, the ground plane under the a/d may contain serrations to steer currents in predictable directions where cross-coupling between analog and digital would otherwise be unavoidable. the ad9221/ad9223/ad9220/eb ground layout, shown in figure 65, depicts the serrated type of arrangement. the analog and digital grounds are connected by a jumper below the a/d. analog and digital supply decoupling the ad9221/ad9223/ad9220 features separate analog and digital supply and ground pins, helping to minimize digital corruption of sensitive analog signals. in general, avdd, the analog supply, should be decoupled to avss, the analog com- mon, as close to the chip as physically possible. figure 56 shows the recommended d ecoupling for the analog supplies; 0.1 m f ceramic chip capac itors should provide adequately low impedance over a wide frequency range. note that the avdd and avss pins are co-located on the ad9221/ad9223/ad9220 to simplify the layout of the decoupling capacitors and provide the shortest possible pcb trace lengths. the ad9221/ad9223/ ad9220/eb power plane layout, shown in figure 66 depicts a typical arrangement using a multilayer pcb. 0.1 m f avdd avss 26 ad9221/ ad9223/ ad9220 25 0.1 m f avdd avss 15 16 figure 56. analog supply decoupling the cml is an internal analog bias point used internally by the ad9221/ad9223/ad9220. this pin must be decoupled with at least a 0.1 m f capacitor as shown in figure 57. the dc level of clock is generated from another type of source (by gating, divid- ing, or other method), it should be retimed by the original clock at the last step. most of the power dissipated by the ad9221/ad9223/ad9220 is from the analog power supplies. however, lower clock speeds will reduce digital current slightly. figure 55 shows the relation- ship between power and clock rate for each a/d. clock frequency C mhz 66 64 56 3.0 power C mw 2.5 62 60 58 5v p-p 2v p-p 54 52 50 48 2.0 1.5 1.0 0.5 figure 55a. ad9221 power consumption vs. clock frequency clock frequency C mhz 125 120 105 6 power C mw 5 115 110 5v p-p 2v p-p 100 95 90 4 3 2 1 0 figure 55b. ad9223 power consumption vs. clock frequency clock frequency C mhz 300 240 12 power C mw 10 280 260 input = 5v p-p input = 2v p-p 220 200 8 6 4 2 014 figure 55c. ad9220 power consumption vs. clock frequency
ad9221/ad9223/ad9220 rev. c C22C cml is approximately avdd/2. this voltage should be buff- ered if it is to be used for any external biasing. 0.1 m f cml ad9221/ ad9223/ ad9220 22 figure 57. cml decoupling the digital activity on the ad9221/ad9223/ad9220 chip falls into two general categories: correction logic, and output drivers. the internal correction logic draws relatively small surges of current, mainly during the clock transitions. the output drivers draw large current impulses while the output bits are changing. the size and duration of these currents are a function of the load on the output bits: large capacitive loads are to be avoided. note, the internal correction logic of the ad9221, ad9223 and ad9220 is referenced to avdd while the output drivers are referenced to dvdd. the decoupling shown in figure 58, a 0.1 m f ceramic chip capacitor, is appropriate for a reasonable capacitive load on the digital outputs (typically 20 pf on each pin). applications in volv- ing greater digital loads should consider increasing the digital decoupling proportionally, and/or using external buffers/latches. 0.1 m f dvdd dvss 28 ad9221/ ad9223/ ad9220 27 figure 58. digital supply decoupling a complete decoupling scheme will also include large tantalum or electrolytic capacitors on the pcb to reduce low-frequency ripple to negligible levels. refer to the ad9221/ad9223/ ad9220/eb schematic and layouts in figures 62C68 for more information regarding the placement of decoupling capacitors. applications direct if down conversion using the ad9220 as previously noted, the ad9220s performance in the differen- tial mode of operation extends well beyond its baseband region and into several nyquist zone regions. hence, the ad9220 may be well suited as a mix down converter in both narrow and wideband applications. various if frequencies exist over the frequency range in which the ad9220 maintains excellent dy- namic performance (e.g., refer to figure 43 and 44). the if signal will be aliased to the adcs baseband region due to the sampling process in a similar manner that a mixer will down convert an if signal. for signals in various nyquist zones, the following equation may be used to determine the final frequency after aliasing. f 1 nyquist = f signal f 2 nyquist = f sample C f signal f 3 nyquist = abs (f sample C f signal ) f 4 nyquist = 2 f sample C f signal f 5 nyquist = abs (2 f sample C f signal ) there are several potential benefits in using the adc to alias (i.e., or mix) down a narrowband or wideband if signal. first and foremost is the elimination of a complete mixer stage with its associated amplifiers and filters, reducing cost and power dissipation. second is the ability to apply various dsp tech niques to perform such functions as filtering, channel selection, quadra- ture demodulation, data reduction, and detection. one common example is the digitization of a 21.4 mhz if using a low jitter 10 mhz sample clock. using the equation above for the fifth nyquist zone, the resultant frequency after sampling is 1.4 mhz. figure 59 shows the typical performance of the ad9220 operating under these conditions. figure 60 demon- strates how the ad9220 is still able to maintain a high degree of linearity and sfdr over a wide amplitude. frequency C mhz 0 C120 15 amplitude C db C40 C60 C80 C20 C100 1 7 8 6 9 2 5 3 4 encode = 10msps a in = 21.4mhz figure 59. if sampling a 21.4 mhz input using the ad9220 (v cm = 2.5 v, input span = 2 v p-p) a in ?db ?0 ?0 ?0 ?0 ?0 0 90 80 0 s/s d 40 30 20 10 60 50 70 sfdr snr figure 60. ad9220 differential input snr/sfdr vs. input amplitude (a in ) @ 21.4 mhz multichannel data acquisition with autocalibration the ad9221/ad9223/ad9220 is well suited for high perfor- mance, low power data acquisition systems. aside from its ex- ceptional ac performance, it exhibits true 12-bit linearity and temperature drift performance (i.e., excluding internal refer- ence). furthermore, the a/d product family provides the system designer with an upward or downward component selection path based on power consumption and sampling rate. a typical multichannel data acquisition system is shown in fig- ure 61. also shown is some additional inexpensive gain and offset autocalibration circuitry which is often required in high accuracy data acquisition systems. these additional peripheral components were selected based on their performance, power consumption, and cost.
ad9221/ad9223/ad9220 rev. c C23C referring to figure 61, the ad9221/ad9223/ad9220 is config- ured for single-ended operation with a 2.5 v p-p input span and a 2.5 v common-mode voltage using an external, precision 2.5 voltage reference, u1. this configuration and input span allows the buffer amplifier, u4, to be single supply. also, it s implifies the design of the low temperature drift autocalibration circuitry which uses thin-film resistors for temperature stability and ratio- metric accuracy. the input of the ad9221/ad9223/ad9220 can be easily configured for a wider span but it should remain within the input/output swing capabilities of a high speed, rail- to-rail, single-supply amplifier, u4 (e.g., ad8041). the gain and offset calibration circuitry is based on two 8-bit, current-output dac08s, u3 and u5. the gain calibration circuitry consisting of u3, and an op amp, u2a, is configured to provide a low drift nominal 1.25 v reference to the ad9221/ ad9223/ad9220. the resistor values which set the gain cali- bration range were selected to provide a nominal adjustment span of 128 lsbs with 1 lsb resolution with respect to the a/d. note that the bandwidth of the reference is low and, as a result, it is not possible to change the reference voltage rapidly in this mode. the offset calibration circuitry consists of a dac, u5 and the buffer amplifier, u4. the dac is configured for a bipolar ad- justment span of 64 lsb with a 1/2 lsb resolution span with respect to the ad9221/ad9223/ad9220. note that both cur- rent outputs of u5 were configured to provide a bipolar adjust- ment span. also, r c is used to decouple the output of both dacs, u3 and u5, from their respective op amps. the calibration procedure consists of a two step process. first, the bipolar offset is calibrated by selecting ch2, the 2.5 v sys- tem reference, of the analog multiplexer and preloading the dac, u5, with a midscale code of 1000 0000. if possible, sev- eral readings of the a/d should be taken and averaged to deter- mine the required digital offset adjustment code, u5. this averaged offset code requires an extra bit of resolu tion since 1 lsb of u5 equates to 1/2 lsb of the ad9221/ad9223/ad9220. the required offset correction code to u5 can then be deter- mined. second, the system gain is calibrated by selecting ch2, a 1.25 v input which corresponds to Cf s of the a/d. before the value is read, u4 should be preloaded with a code of 00 (hex). several readings can also be taken and averaged to determine the digital gain adjustment code to u2a. in this case, 1 lsb of the a/d corresponds to 1 lsb of u4. due to the ad9221/ad9223/ad9220s excellent inl perfor- mance, a two-point calibration procedure (i.e., Cf s to midscale) instead of an endpoint calibration procedure was chosen. also, since the bipolar offset is insensitive to any gain adjustment (due to the differential sha of the a/d), an iterative calibration process is not required. the temperature stability of the circuit is enhanced by selecting a dual precision op amp for u2 (e.g., op293) and low temperature drift, thin film resistors. note that this application cir cuit was not built at the release of this data sheet. please consult analog devices for application assis- tance or comments. 1.25k v 0.1 m f 10 m f 2.5k v 2.5k v +5v u1 ref43 vref(+) vref(C) u3 dac08 iout iout 0.1 m f 2.5k v 0.1 m f 2.5k v 0.1 m f 2.5k v 162 v 2.5k v r c 100 v 1.1k v 2 3 39 v u2a 1.25v 6 39mv u2b ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 u6 adg608 1.25v out vref(+) vref(C) u5 dac08 iout iout u4 2.5k v r c 100 v 39 v ad9221/ ad9223/ ad9220 sense vref vina vinb bit 1 C bit 12 otr 2.50v r c 100 v 2.5k v 39 v figure 61. typical multichannel data acquisition system
ad9221/ad9223/ad9220 rev. c C24C figure 62. evaluation board schematic r14 50 v clk in 5 6 u8 74hc04n 4 3 u8 74hc04n clk jp15 clk jp16 tpe jp21 r12 10k v jp11 r28 22 v 33 j8 tp3 r27 22 v 39 j8 tp4 r26 22 v 23 j8 tp5 r25 22 v 21 j8 tp6 r24 22 v 19 j8 tp7 r23 22 v 17 j8 tp8 r22 22 v 15 j8 tp9 r21 22 v 13 j8 tp10 r20 22 v 11 j8 tp11 r19 22 v 9j8 tp12 r18 22 v 7j8 tp13 r17 22 v 5j8 tp14 r16 22 v 3j8 tp15 r15 22 v 1 j8 tp16 a c20 0.1 m f c19 0.1 m f c16 10 m f 16v a c28 0.1 m f y2b y3b y4b y5b y6b y7b y0a y1a y2a y3a y4a y5a jp20 jp19 13 14 15 16 17 18 11 12 y0a y1a y2a y3a y4a y5a c21 0.1 m f +5d2 y5 y4 y3 y2 y1 y0 y7 y6 +5vd g1 g2 a7 a6 a5 a4 a3 a2 a1 a0 gnd u6 74hc541n 8 7 6 5 4 3 2 10 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 msb 1 19 9 tpd c33 0.1 m f jp13 +5a jp12 jp14 r13 10k v c17 0.1 m f tpc d5 1n5711 a a c15 15pf not installed remove for diff. mode a a c14 0.1 m f tpb jp10 refout vinb d4 1n5711 +5a c18 0.1 m f +5a 20 msb otr bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 lsb ad9221/ ad9223/ ad9220 13 14 12 11 10 9 8 7 6 5 4 3 2 1 11 12 13 14 15 16 17 18 y2b y3b y4b y5b y6b y7b c22 0.1 m f +5d2 74hc541n 8 7 6 5 4 3 2 10 otr lsb bit 11 bit 10 bit 9 bit 8 1 19 9 20 y7 y6 y5 y4 y3 y2 y1 y0 +5vd g1 g2 a7 a6 a5 a4 a3 a2 a1 a0 gnd u7 12 u8 74hc04n msb avdd avdd vina capb capt cml vinb vref sense refcom dvss dvdd avss avss bit 1 otr bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 clk u5 15 26 23 20 21 22 24 18 17 19 27 28 25 16 d3 1n5711 a c13 15pf tpa vina d2 1n5711 not installed a c26 0.1 m f c25 0.1 m f c24 10 m f 16v c23 0.1 m f jp17 jp18 j7 tp1 agnd dgnd a +5d a +5a 2j8 4j8 6j8 8j8 10 j8 12 j8 14 j8 16 j8 18 j8 20 j8 22 j8 24 j8 25 j8 26 j8 27 j8 28 j8 29 j8 30 j8 31 j8 32 j8 34 j8 35 j8 36 j8 37 j8 38 j8 40 j8 nc nc j2 +v cc a c32 0.1 m f a c29 22 m f 25v tpf l5 +supply jp6 j3 Cv ee tpg a c30 22 m f 25v +5 dig tph a c31 22 m f 25v j4 dgnd tpi j5 jp7 a c4 0.1 m f c5 0.1 m f l6 l2 l3 l4 c6 0.1 m f gj1 agnd tpj j6 a tpk tpl (gj1-wire jumper ckt side) power supply +5refbuf Csupply +5d +5d2 l1 +5a u2 in out gnd 1 3 78l05p 2 a a c12 0.1 m f r9 50 v 6 7 2 3 4 +5refbuf ad817 a c34 0.1 m f Csupply jp9 r7 15k v a c7 0.1 m f a r8 10k v f.s./gain adj c8 10 m f 16v external reference and reference buffer u4 a r11 1k v c9 0.1 m f r29 316 v a q1 2n2222 a c10 10 m f 16v a c11 0.1 m f refout +5refbuf r10 820 v +5refbuf a u3 v in v out gnd 6 2 4 ref43 +5d2 c27 0.1 m f u8 decoupling a vina c2 0.1 m f r3 261 v 6 7 2 3 4 u1 +supply ad8047 a c1 0.1 m f Csupply jp2 r2 261 v jp1 jp5 a c3 0.1 m f r5 10k v r6 10k v r4 33 v jp4 jp3 r1 50 v a j1 ain vinb a 9 8 u8 74hc04n 11 10 u8 74hc04n 13 12 u8 74hc04n spare gates a a
ad9221/ad9223/ad9220 rev. c C25C figure 63. evaluation board component side layout (not to scale) figure 64. evaluation board solder side layout (not to scale)
ad9221/ad9223/ad9220 rev. c C26C figure 65. evaluation board ground plane layout (not to scale) figure 66. evaluation board power plane layout
ad9221/ad9223/ad9220 rev. c C27C figure 67. evaluation board component side silkscreen (not to scale) figure 68. evaluation board component side silkscreen (not to scale)
ad9221/ad9223/ad9220 rev. c C28C c2127cC0C3/99 printed in u.s.a. outline dimensions dimensions shown in inches and (mm). 28-lead soic (r-28) 28 15 14 1 0.7125 (18.10) 0.6969 (17.70) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc

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